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ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 0 ? revision history revision description issue date rev. 1.0 initial issued 2012 / 2/22 rev. 1.1 rev. 1.2 rev. 1.3 ?ce# R v cc - 0.2v? revised as ?ce# Q 0.2? for test condition of average operating power supply current icc1 on page3 2.revised ordering information page13 1. revise ?test condition? for voh, vol on page 4 i oh = -8ma revised as -4ma i ol =4ma revised as 8ma 2. revise vih(max) & vil(min) note on page 4 vih(max) = vcc + 2.0v for pulse width less than 6ns. vil(min) = vss - 2.0v for pulse width less than 6ns. revised the address pin sequence of tsop-ii pin configuration on page 2 in order to be compatible with industry convention. (no function specifications and applications have been changed and all the characteristics are kept all the same as rev 1.2 ) jul y .19. 2012 june. 04. 2013 oct. 30. 2013
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 1 ? features ? fast access time : 8/10/12ns ? low power consumption: operating current: 90/80/70ma (typ. 8/10/12ns) standby current: 3ma(typ) ? single 3.3v power supply ? all inputs and outputs ttl compatible ? fully static operation ? tri-state output ? data byte control : lb# (dq0 ~ dq7) ub# (dq8 ~ dq15) ? data retention voltage : 1.5v (min.) ? green package available ? package : 44-pin 400 mil tsop-ii 48-ball 6mmx8mm tfbga general description the ly61l51216a is a 8m-bit high speed cmos static random access memory organized as 512k words by 16 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the ly61l51216a operates from a single power supply of 3.3v and all inputs and outputs are fully ttl compatible product family product family operating temperature vcc range speed power dissipation standby(i sb1, typ.) operating(icc 1 ,typ.) ly61l51216a 0 ~ 70 3.0 ~ 3.6v 8/10/12ns 3ma 90/80/70ma ly61l51216a(i) -40 ~ 85 3.0 ~ 3.6v 8/10/12ns 3ma 90/80/70ma ly61l51216a 0 ~ 70 2.7 ~ 3.6v 10/12ns 3ma 80/70ma ly61l51216a(i) -40 ~ 85 2.7 ~ 3.6v 10/12ns 3ma 80/70ma functional block diagram pin description symbol description a0 - a18 address inputs dq0 ? dq15 data inputs/outputs ce# chip enable input we# write enable input oe# output enable input lb# lower byte control ub# upper byte control v cc power supply v ss ground
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 2 ? pin configuration tfbga nc a3 a10 a9 a11 a0 a14 a8 nc we# dq9 dq14 dq15 a18 vss nc a13 dq8 vcc vcc dq7 a15 vss ce# lb# dq6 dq2 dq0 a2 oe# a1 a6 a5 a4 ub# 123456 h g c d e f a b a12 nc a17 a7 a16 dq10 dq11 dq12 dq13 dq5 dq4 dq3 dq1 absolute maximun ratings* parameter symbol rating unit terminal voltage with respect to v ss v term -0.5 to 4.6 v operating temperature t a 0 to 70(c grade) -40 to 85(i grade) storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 sec) t solder 260 *stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above t hose indicated in the operati onal sections of this s pecification is not implied. exposure to the absolute ma ximum rating conditions for extended per iod may affect device reliability.
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 3 ? truth table mode ce# oe# we# lb# ub# i/o operation supply current dq0-dq7 dq8-dq15 standby h x x x x high ? z high ? z i sb1 output disable l l h x h x x h x h high ? z high ? z high ? z high ? z i cc read l l l l l l h h h l h l h l l d out high ? z d out high ? z d out d out i cc write l l l x x x l l l l h l h l l d in high ? z d in high ? z d in d in i cc note: h = v ih , l = v il , x = don't care. dc electrical characteristics parameter symbol test condition min. typ. * 4 max. unit supply voltage v cc -8 3.0 3.3 3.6 v -10/12 2.7 3.3 3.6 v input high voltage v ih *1 2.2 - v cc +0.3 v input low voltage v il *2 - 0.3 - 0.8 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v out R v ss , output disabled - 1 - 1 a output high voltage v oh i oh = -4m a 2.4 - - v output low voltage v ol i ol =8ma - - 0.4 v average operating power supply current icc ce# = v il , i i/o = 0ma ;f=max -8 - 110 140 ma -10 - 100 130 ma -12 - 90 120 m a icc 1 ce# Q 0.2, other pin is at 0.2v or vcc-0.2v i i/o = 0ma;f=max -8 - 90 120 ma -10 - 80 110 ma -12 - 70 100 ma standby power supply current isb ce# R vih ,other pin is at vil or vih - - 40 ma standby power supply current i sb1 ce# v R cc -0.2v; other pin is at 0.2v or vcc-0.2v - 3 25 ma notes: 1. v ih (max) = v cc + 2.0v for pulse width less than 6ns. 2. v il (min) = v ss - 2.0v for pulse width less than 6ns. 3. over/undershoot specifications ar e characterized on engineering evaluati on stage, not for mass production test. 4. typical values are included for reference only and are not guaranteed or tested. typical valued are measured at v cc = v cc (typ.) and t a = 25
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 4 ? capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. ma x unit input capacitance c in - 8 pf input/output capacitance c i/o - 10 pf note : these parameters are guaranteed by devic e characterization, but not production tested. ac test conditions speed 8ns/10/12ns input pulse levels 0.2v to vcc-0.2v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf + 1ttl, i oh /i ol = -4ma/8ma ac electrical characteristics (1) read cycle parameter sym. ly61l51216a-8 ly61l51216a-10 ly61l51216a-12 unit min. max. min. max. min. max. read cycle time t rc 8 - 10 - 12 - ns address access time t aa - 8 - 10 - 12 ns chip enable access time t ace - 8 - 10 - 12 ns output enable access time t oe -4.5-4.5- 5 ns chip enable to output in lo w -z t clz *2-2-3 - ns output enable to output in lo w -z t olz *0-0-0 - ns chip disable to output in high-z t chz *-3-4- 5 ns output disable to output in high-z t ohz *-3-4- 5 ns output hold from address change t oh 2-2-2 - ns lb#, ub# access time t ba -4.5-4.5- 5 ns lb#, ub# to high-z output t bhz *-3-4- 5 ns lb#, ub# to lo w -z output t blz *0-0-0 - ns (2) write cycle parameter sym. ly61l51216a-8 ly61l51216a-10 ly61l51216a-12 unit min. max. min. max. min. max. write cycle time t wc 8 - 10 - 12 - ns address valid to end of write t aw 6.5 - 8 - 10 - ns chip enable to end of write t cw 6.5 - 8 - 10 - ns address set-up time t as 0-0-0 - ns write pulse width t wp 6.5 - 8 - 10 - ns write recovery time t wr 0-0-0 - ns data to write time overlap t dw 5-6-7 - ns data hold from end of write time t dh 0-0-0 - ns output active from end of write t ow *2-2-2 - ns write to output in high-z t whz *-3-4- 5 ns lb#, ub# valid to end of write t bw 6.5 - 8 - 10 - ns *these parameters are guaranteed by device c haracterization, but not production tested.
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 5 ? timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 (ce# and oe# controlled) (1,3,4,5) dout data valid high-z high-z t clz t olz t chz t ohz t oh oe# t oe lb#,ub# t bhz t ace ce# t aa address t rc t ba t blz notes : 1.we#is high for read cycle. 2.device is continuously selected oe# = low, ce# = low, lb# or ub# = low . 3.address must be valid prior to or coincident with ce# = low, lb# or ub# = low transition; otherwise t aa is the limiting parameter. 4.t clz , t blz, t olz , t chz, t bhz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t bhz is less than t blz , t ohz is less than t olz.
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 6 ? write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw t wr t as (4) t ow lb#,ub# ce# t aw address t wc t bw write cycle 2 (ce# controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# lb#,ub# t cw ce# address t wr t as t aw t wc t wp t bw
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 7 ? write cycle 3 ( lb#,ub# controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# lb#,ub# t cw ce# address t wr t as t aw t wc t wp t bw notes : 1.we#,ce#, lb#, ub# must be high during all address transitions. 2.a write occurs during the overlap of a low ce#, low we#, lb# or ub# = low. 3.during a we# controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce#, lb#, ub# low transition occurs simultaneously with or after we# low transition, the outputs remain in a high impe dance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state. data retention characteristics parameter symbol test cond ition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v 1.5 - 3.6 v data retention current i dr v cc = 1.5v ce# v R cc - 0.2v; other pin is at 0.2v or vcc-0.2v - - 3 25 ma chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform vcc ce# v dr R 1.5v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.)
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 8 ? package outline dimension 44-pin 400mil tsop- package outline dimension symbols dimensions in millmeters dimensions in mils min. nom. max. min. nom. max. a - - 1.20 - - 47.2 a1 0.05 0.10 0. 15 2.0 3.9 5.9 a2 0.95 1.00 1. 05 37.4 39.4 41.3 b 0.30 - 0.45 11.8 - 17.7 c 0.12 - 0.21 4.7 - 8.3 d 18.212 18.415 18.618 717 725 733 e 11.506 11.760 12.014 453 463 473 e1 9.957 10.160 10.363 392 400 408 e - 0.800 - - 31.5 - l 0.40 0.50 0. 60 15.7 19.7 23.6 zd - 0.805 - - 31.7 - y - - 0.076 - - 3 0 o 3 o 6 o 0 o 3 o 6 o
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 9 ? 48-ball 6mm 8mm tfbga package outline dimension
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 10 ? ordering information package type access time (speed)(ns) temperature range( ) packing type lyontek item no. 44pin(400mil) tsop-ii 8 0 ~70 tray ly61l51216aml-8 tape reel ly61l51216aml-8t -40 ~85 tray ly61l51216aml-8i tape reel ly61l51216aml-8it 10 0 ~70 tray ly61l51216aml-10 tape reel ly61l51216aml-10t -40 ~85 tray LY61L51216AML-10I tape reel LY61L51216AML-10It 12 0 ~70 tray ly61l51216aml-12 tape reel ly61l51216aml-12t -40 ~85 tray ly61l51216aml-12i tape reel ly61l51216aml-12it 48-ball(6mmx8mm) tfbga 8 0 ~70 tray ly61l51216agl-8 tape reel ly61l51216agl-8t -40 ~85 tray ly61l51216agl-8i tape reel ly61l51216agl-8it 10 0 ~70 tray ly61l51216agl-10 tape reel ly61l51216agl-10t -40 ~85 tray ly61l51216agl-10i tape reel ly61l51216agl-10it 12 0 ~70 tray ly61l51216agl-12 tape reel ly61l51216agl-12t -40 ~85 tray ly61l51216agl-12i tape reel ly61l51216agl-12it
ly61l51216a rev. 1.3 512k x 16 bit high speed cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, lndustry e . rd. 9, science- based industrial park, hsinchu 300, taiwan tel: 886-3-6668838 fax: 886-3-6668836 11 ? this page is left blank intentionally.

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